In this project, learners design a custom AI accelerator optimized for image classification workloads such as CNN inference. You will architect compute units, design matrix multiplication engines, optimize memory access patterns, and implement RTL modules. The project includes performance comparison against CPU/GPU baselines, analysis of throughput and latency, and basic RTL-to-GDS flow exposure. By the end, you gain hands-on experience in AI chip architecture, hardware acceleration, memory optimization, and practical silicon design concepts used in real-world AI processors.

This project focuses on building an autonomous EDA orchestration framework using AI agents. You will create agents that control synthesis, floorplanning, placement, routing, and timing analysis. The system automatically reads reports, identifies bottlenecks, applies optimization strategies, and iterates until targets are met. This simulates next-generation chip design workflows where AI manages EDA tools. Learners gain experience in agentic systems, Python automation, tool integration, feedback loops, and intelligent RTL-to-GDS optimization pipelines.

In this project, you develop machine learning models to predict timing slack and power consumption from design parameters such as cell density, routing congestion, and clock frequency. These predictions guide placement and optimization decisions. You’ll implement data pipelines, train ML models, and integrate predictions into the design flow. This project demonstrates how AI improves silicon PPA (Power, Performance, Area) and teaches design space exploration, ML-driven optimization, and practical applications of AI in semiconductor engineering.