UART (Universal Asynchronous Receiver-Transmitter) is a fundamental serial communication protocol used in embedded chips, IoT devices, and ASIC SoCs across the semiconductor industry. In this project, you design a fully configurable UART controller in synthesizable Verilog HDL — including the baud rate generator, transmitter, and receiver modules. You write testbenches, run RTL simulation on industry-standard tools, perform logic synthesis, and validate the final design on FPGA hardware to confirm real-time serial communication. This project mirrors the kind of RTL coding and hardware validation work done by engineers at companies like Texas Instruments and NXP Semiconductors.

The 32-bit RISC processor is the architecture behind modern ARM-based chips, mobile SoCs, and embedded processors powering billions of devices globally. In this project, you implement a fully pipelined RISC processor using RTL design methodology — covering all five stages: Fetch, Decode, Execute, Memory, and Writeback. You build hazard detection and data forwarding logic, simulate the full processor using VCS or ModelSim, and run synthesis and timing analysis to generate real ASIC design reports. This is considered one of the most valuable RTL portfolio projects for engineers targeting roles at ASIC and SoC design companies.

Clock Domain Crossing (CDC) is one of the most commonly tested concepts in RTL Design Engineer interviews at companies like Qualcomm, Broadcom, and Intel. In this project, you design a dual-clock asynchronous FIFO in Verilog — implementing Gray code pointer logic, a 2-flip-flop synchronizer, and full/empty flag generation to safely transfer data between two independent clock domains. You simulate the design, verify data integrity across clock boundaries, and perform Static Timing Analysis (STA) to confirm reliable operation in high-speed digital systems. This project directly builds the CDC and STA skills that semiconductor companies test in technical interviews.