Design and implement a traffic light controller using FSM concepts. The project involves creating state diagrams, state transitions, and timing sequences for traffic signals at an intersection. Learners will develop RTL code, simulate functionality, and verify proper operation under different traffic conditions. This project helps build a strong understanding of sequential logic design, state machine implementation, and timing control techniques commonly used in VLSI and embedded systems.

Develop a synchronous FIFO memory controller capable of handling data storage and retrieval operations efficiently. The project includes implementing read/write pointers, full and empty status detection, and data management logic. Students will create RTL designs, perform simulations, and validate memory operations. This project provides hands-on experience with memory architectures, data buffering techniques, and RTL design practices widely used in communication and semiconductor applications.

Design a pipelined ALU capable of performing arithmetic and logical operations such as addition, subtraction, multiplication, comparison, and bitwise functions. The project focuses on improving performance through pipelining techniques while maintaining accurate operation across multiple stages. Learners will write RTL code, verify functionality through simulation, and analyze timing behavior. This project develops practical skills in high-performance digital design, pipelined architectures, and processor-oriented hardware development.