This project focuses on designing a smart traffic signal controller using Verilog HDL and FPGA technology. The system monitors traffic density from multiple road inputs and dynamically adjusts signal timings to improve traffic flow and reduce congestion. Students will learn Finite State Machine (FSM) design, RTL coding, simulation, synthesis, and timing analysis. The project provides practical exposure to real-time digital system development and demonstrates how VLSI concepts are applied in intelligent transportation systems used in modern smart cities.

The FPGA-Based Secure Electronic Door Lock System is designed to provide secure access control using a password authentication mechanism. Users enter a predefined password, and the system grants or denies access based on verification results. The project involves Verilog coding, FSM implementation, digital logic design, simulation, and hardware testing on FPGA platforms. Students gain hands-on experience in designing secure digital systems and understanding how VLSI technology is used in security, automation, and smart building applications.

This project involves developing a low-power digital clock capable of displaying real-time information while supporting alarm and countdown timer functions. The design emphasizes power-efficient digital circuit techniques, making it suitable for battery-operated devices. Students will work with RTL design, clock management, counters, timing circuits, simulation, and FPGA implementation. The project helps learners understand practical VLSI design methodologies and power optimization strategies widely used in consumer electronics, embedded systems, and IoT devices.