Design and implement an intelligent elevator controller using Finite State Machine (FSM) concepts. The system manages floor requests, door operations, movement direction, and safety conditions. Students will develop RTL code, perform simulation, and verify functionality under multiple operating scenarios. This project provides practical experience in sequential logic design, state machine implementation, and real-world control systems commonly used in VLSI applications.

Develop a high-speed synchronous FIFO controller for efficient data buffering and transfer between digital modules. The project includes implementing read/write operations, full and empty flag generation, pointer management, and overflow protection. Learners will create RTL designs, run simulations, and analyze timing behavior. This project strengthens knowledge of memory architectures, data communication, and RTL design techniques used in ASIC and FPGA development.

Design a simplified pipelined RISC processor core capable of executing arithmetic, logical, and data transfer instructions. The project focuses on instruction execution, pipeline stages, control logic, and performance optimization. Students will write RTL code, verify processor functionality, and evaluate timing performance. This industry-oriented project helps learners understand processor architecture, pipelining concepts, and advanced digital design methodologies widely used in semiconductor companies.