Develop and verify a Smart Traffic Signal Controller using Verilog, SystemVerilog, and UVM methodologies to manage traffic flow efficiently at busy intersections in Powai, Mumbai. The project focuses on RTL design, FSM implementation, timing analysis, and functional verification of traffic signal operations under different traffic conditions. Learners will create comprehensive testbenches, assertions, and coverage models to validate system performance. This project provides practical exposure to ASIC and FPGA design concepts while simulating real-world smart city traffic management applications commonly used in urban areas like Powai and surrounding Mumbai technology hubs.

Design and verify an FPGA-based Metro Access Control System for metro stations across Navi Mumbai using Verilog HDL and SystemVerilog. The system manages passenger entry validation, ticket authentication, gate control, and access monitoring. Participants will implement RTL modules, perform functional verification using UVM, and conduct timing analysis to ensure reliable operation. This project helps learners understand real-time digital design challenges while gaining hands-on experience in RTL Design and Verification Training in Mumbai. The solution is inspired by the growing transportation infrastructure across Navi Mumbai and nearby commercial corridors.

Build and verify a High-Speed Parking Management Controller designed for commercial complexes and IT parks in Andheri, Mumbai. The project involves creating RTL modules for vehicle detection, parking slot allocation, occupancy tracking, and automated entry-exit control using Verilog and SystemVerilog. Verification engineers will develop UVM-based test environments, assertions, and coverage-driven verification strategies to validate functionality. This industry-oriented project reflects real-world applications found in Mumbai's business districts and provides valuable experience in ASIC verification, FPGA implementation, and digital system design for modern smart infrastructure solutions.