Design and implement a Universal Asynchronous Receiver Transmitter (UART) controller using RTL methodology. The project includes transmitter and receiver modules, baud rate generation, serial-to-parallel conversion, and error detection mechanisms. Learners will develop synthesizable RTL code, perform functional verification, and validate data communication between digital systems. This project provides practical exposure to communication protocols commonly used in FPGA and ASIC designs.

Develop an SDRAM controller capable of managing memory initialization, read/write operations, refresh cycles, and address management. The project focuses on designing efficient control logic and timing sequences to ensure reliable memory access. Students will create RTL code, perform simulations, and analyze controller performance. This project helps build expertise in memory subsystem design, timing management, and semiconductor hardware development.

Design a smart vending machine controller using Finite State Machine (FSM) architecture. The system should accept different coin values, validate transactions, dispense products, and return change when necessary. Learners will implement the complete control logic in RTL, simulate various user scenarios, and verify functional correctness. This project develops skills in FSM design, digital control systems, RTL coding, and hardware implementation techniques used in real-world applications.