This project focuses on designing an FPGA-based intelligent traffic light control system optimized for urban congestion in Kolkata, especially around Salt Lake Sector V IT hub. The system dynamically adjusts signal timing based on vehicle density using Verilog HDL. It simulates real-time traffic scenarios and improves flow efficiency in high-density city regions. This project is ideal for understanding FPGA implementation, RTL design, and real-time embedded system behavior in smart city infrastructure.

This project involves designing a low-power Arithmetic Logic Unit (ALU) using Verilog HDL optimized for energy-efficient semiconductor applications in New Town Kolkata tech zone. It includes arithmetic and logical operations with power optimization techniques like clock gating and operand isolation. The project is widely relevant for ASIC design flow learning and helps students understand how modern chip designs reduce power consumption in mobile and IoT devices.

This project covers the complete RTL design, simulation, and verification of an 8-bit processor using Verilog/SystemVerilog targeted for embedded system applications in the Rajarhat Kolkata region. It includes instruction decoding, ALU integration, and testbench creation for functional verification. This project helps learners understand CPU architecture, verification methodologies, and real-world semiconductor design flow used in embedded and SoC industries.