This project focuses on designing and verifying an AXI-based memory controller using Verilog/SystemVerilog as part of JastTech’s VLSI training in Noida. The design includes address decoding, burst transfer handling, and read/write arbitration. A UVM-based verification environment is developed to validate functional correctness, transaction flow, and protocol compliance. The project simulates real-world semiconductor industry scenarios used in Noida and NCR companies, making it highly relevant for RTL Design Engineer and Verification Engineer roles.

This project involves designing a traffic light controller using FPGA technology as part of JastTech VLSI training in Noida. The system is implemented using Verilog HDL and deployed on FPGA hardware to simulate real-time traffic management for smart city applications in Noida regions like Sector 62 and Greater Noida. It demonstrates finite state machine (FSM) design, timing control, and hardware debugging techniques, making it ideal for FPGA Engineer and Embedded Hardware roles.

This project focuses on building a complete UVM-based verification environment for a UART communication protocol as part of JastTech’s VLSI training in Noida. It includes stimulus generation, driver-monitor architecture, scoreboard checking, and functional coverage analysis. The project replicates real-world chip verification scenarios used in semiconductor companies across Noida and Greater Noida IT hubs, preparing candidates for high-demand Verification Engineer roles in the VLSI industry.